This invention broadly relates to thin film transistors, thin film transistor arrays, and to a method of preparing the same. More particularly, the invention concerns a complete photolithographic process for fabricating thin film transistors and thin film transistor arrays in which the critical, and contamination vulnerable, semiconductor-insulator interfaces are formed in a single vacuum pump-down.
Thin film transistors, and particularly an array of thin film transistors continue to be attractive drivers for active display panels, such as those incorporating liquid crystal or electroluminescent media. Because of the resolution achievable, photolithographic processes are particularly advantageous in the preparation of the high density thin film transistor arrays needed for such display panels.
It is well known to those practicing this art that the electrical performance and stability of thin film transistors are critically dependent upon the quality of the interfaces between the various layers of material forming the devices. Of special importance are the interfaces between the semiconductor and adjacent layers. It is also well known that the quality of these interfaces is greatest when the interfaces are prepared in a single vacuum pump-down operation.
The early efforts to employ a single pump-down technique focused upon the use of a multiple number of shadow masks within a vacuum system in order to deposit the proper shapes of the various component layers of the thin film transistors. These early multiple shadow mask processes are not altogether satisfactory, however, because of such problems as mask to mask registration and low resolution.
The problems occasioned by the use of multiple shadow masks are avoided in the process disclosed in U.S. Pat. No. 4,331,758 to Luo. In the disclosed process, during a single pump-down, a uniform layer of a semiconducting material is deposited onto a substrate. Thereafter, without breaking vacuum, a plurality of discrete areas of an insulating material is deposited onto the semiconductor layer through a single shadow mask. Then a uniform layer of a conducting material is deposited over the areas of insulating material and exposed portions of the semiconductive layer.
Yet another sequence for fabricating thin film transistors with a single shadow mask, single pump-down technique is shown in U.S. Pat. No. 4,335,161 to Luo. In that process, the opening (or openings for formation of thin film transistor arrays) in the mask is commensurate in size and shape to the semiconductor pads to be deposited. This mask is utilized, during a single vacuum pump-down, to deposit the semiconductive pad, the source and drain electrodes, and an insulating layer over the source and drain electrodes and the exposed portion of the semiconductive pad. The mask is moved in a simple bidirectional (180.degree. reciprocating) manner between the successive depositions of the semiconductor material which forms the transistor pad and the conductive material which forms the two electrical contacts to the semiconductor pad.
As suggested hereinabove, photolithographic pattern delineation techniques excel over shadow mask techniques in providing the resolutions required to produce thin film transistor arrays suitable for drivers in high quality pictorial devices. Characteristically, such photolithographic techniques employ wet chemistry processes to selectively define patterned layers of conductive and insulative materials. Artisans skilled in this area recognize that exposure of the sensitive transistor interfaces to such wet processing results in impurity contamination which degrades the quality of the transistor characteristics. Commonly assigned U.S. Pat. No. 4,404,731 to Michael Poleshuk, granted Sept. 20, 1983 discloses a process for overcoming the disadvantages which can arise from exposure of the critical surfaces of the consituent layers of the thin film device to wet processing. This is achieved through the use of a single vacuum pump-down step in which the damage sensitive semiconductor is effectively sealed, or encapsulated, against subsequent wet processing. In the initial steps of this fabrication sequence a gate electrode is formed and covered with a layer of insulator. An additive photoresist mask is then formed for definition of the semiconductor pad. Thereafter, during a single vacuum pump-down, layers of insulator, semiconductor, and conductor (source-drain contact) layers are sequentially deposited to form the critical semiconductor-insulator interface and semi-source and drain contacts. During subsequent lift-off removal of the photoresist mask, the conductive contact layer functions as a protective cap over the semiconductor pad, preventing harmful interaction between the semiconductor and the stripping solution. After mask removal, the thin film transistor is completed by removal of the portion of the contact layer overlying the conducting channel of the semiconductor and definition of the source and drain network.
It has heretofore been recognized that technological problems are encountered in fabricating multi layered thin film transistors and transistor arrays. In particular, step coverage problems are prevalent when attempting to form electrical contact between circuit elements located at different levels. In one configuration of thin film transistors, for example, semiconductor films extend from the substrate level to source and drain pads on the next adjacent level. The gate oxide and electrode must necessarily follow the contour of the semiconductor films. The additional layers needed to complete the array, i.e. gate structures and crossovers, likewise follow the irregularity of this contour, producing a completed device consisting of a multi layered mesas with varied geometries and individual heights. Coverage of these mesas steps with continuous films of uniform thickness poses difficulties because of the sharply defined vertical edges of patterns delineated by processing steps such as photolithographic fabrication. A means for overcoming the step coverage problems is disclosed in commonly assigned, U.S. Pat. No. 4,389,481 to Michael Poleshuk et al. granted June 21, 1983 process disclosed therein, thin film transistors or an array of thin film are formed on a substrate by sequential deposition of a series of layers fabricated such that each element of the transistor structure is disposed in a planar relationship with respect to the next adjacent layer. In accordance with the process, the deposition of each of the elemental members of the thin film transistor structures is immediately followed by filling in the valleys between the elemental structures with an insulating material to form a planar surface. This planar surface, in turn, forms the surface upon which the succeeding planar layer is formed.